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Build, reports, and programming

Behavioral simulation first

Run simulation before synthesis:

  • Compile all design and testbench sources.
  • Elaborate the intended testbench top.
  • Run until finish or a watchdog timeout.
  • Require every assertion to pass.

Waveforms are for diagnosis, not the primary pass/fail mechanism.

Elaborated RTL

Open RTL Analysis → Open Elaborated Design and inspect:

  • Hierarchy.
  • Port widths and directions.
  • Schematic for unexpected latches or combinational feedback.
  • Constant or unconnected logic.
  • Parameter values.

Synthesis

Synthesis translates RTL into device primitives.

Inspect:

  • Synthesis messages and warnings.
  • Inferred latches.
  • Inferred RAM/DSP/shift-register resources.
  • Removed or constant logic.
  • High-fanout nets.
  • Resource utilization.

An unused output can cause an entire correct-looking calculation to be optimized away. Synthesis keeps observable behavior, not source-code effort.

Implementation

Implementation consists mainly of:

  1. Optimization.
  2. Placement of primitives.
  3. Routing of connections.
  4. Physical optimization where requested.
  5. Timing and design-rule analysis.

Routing delay often dominates logic delay in FPGAs. A logically small path can fail if placement and fanout are poor.

Timing sign-off

Open the implemented timing summary and check:

  • All clocks appear with expected periods.
  • Setup WNS is non-negative.
  • Hold slack is non-negative.
  • Pulse-width checks pass.
  • No unexplained unconstrained endpoints exist.
  • Cross-clock paths match the intended CDC architecture.

Do not judge only by the green checkmark beside implementation.

Generate the bitstream

Bitstream generation may run DRC checks. Treat critical warnings seriously:

  • Missing pin locations.
  • Missing I/O standards.
  • Multiple drivers.
  • Unconstrained clocks.
  • Unsafe clock routing.

Program over JTAG

GUI flow:

  1. Open Hardware Manager.
  2. Open Target → Auto Connect.
  3. Select the FPGA.
  4. Program Device.
  5. Choose the current bitstream.

If the board is not found:

  • Confirm power and cable data capability.
  • Confirm the correct USB port.
  • Check Windows device/driver recognition.
  • Close another application holding the JTAG cable.
  • Refresh/open the hardware target.

Reproducible Tcl flow

Vivado actions can be scripted:

read_vhdl -vhdl2008 ../src/top.vhd
read_xdc ../constraints/basys3.xdc
synth_design -top top -part xc7a35tcpg236-1
opt_design
place_design
route_design
report_timing_summary -file timing_summary.rpt
report_utilization -file utilization.rpt
write_bitstream -force top.bit

A production script should stop when commands fail and should check timing/DRC requirements explicitly. The example shows the phase order, not a complete universal build system.

Run in batch:

vivado.bat -mode batch -source build.tcl

Save useful evidence

For a university submission or personal milestone, archive:

  • Source commit or zip.
  • Exact FPGA part and Vivado version.
  • XDC file.
  • Test logs and vector seeds.
  • Timing summary.
  • Utilization report.
  • DRC report.
  • Bitstream, if appropriate.

Generated project caches are much less valuable than scripts and sources capable of recreating them.

Build gate

Use this as a definition of done:

  • All automated simulations pass.
  • No unexpected compile or simulation warnings.
  • Synthesis shows intended resource inference.
  • No unintended latches or multiple drivers.
  • DRC passes.
  • All relevant timing constraints exist.
  • Implementation timing passes.
  • Hardware sanity test passes.