Quick reference

Standard header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Testbench additions:

use std.textio.all;
use std.env.finish;

Entity and architecture

entity block_name is
  generic (
    G_WIDTH : positive := 8
  );
  port (
    clk_i   : in  std_logic;
    reset_i : in  std_logic;
    data_i  : in  unsigned(G_WIDTH - 1 downto 0);
    data_o  : out unsigned(G_WIDTH - 1 downto 0)
  );
end entity;

architecture rtl of block_name is
  signal data_q : unsigned(G_WIDTH - 1 downto 0);
begin
  -- Concurrent region
end architecture;

Direct instantiation

u_name : entity work.block_name(rtl)
  generic map (
    G_WIDTH => 16
  )
  port map (
    clk_i   => clk_i,
    reset_i => reset_i,
    data_i  => input_s,
    data_o  => output_s
  );

Combinational process

process(all)
begin
  y_o <= DEFAULT_VALUE;
  if condition_i = '1' then
    y_o <= selected_i;
  end if;
end process;

Clocked process

process(clk_i)
begin
  if rising_edge(clk_i) then
    if reset_i = '1' then
      q_o <= RESET_VALUE;
    elsif enable_i = '1' then
      q_o <= d_i;
    end if;
  end if;
end process;

Mux

with select_i select
  y_o <= a_i when "00",
         b_i when "01",
         c_i when "10",
         d_i when others;

Conversions

From	To	Expression
integer	unsigned	to_unsigned(value, width)
integer	signed	to_signed(value, width)
unsigned	integer	to_integer(value)
signed	integer	to_integer(value)
std_logic_vector	unsigned	unsigned(value)
std_logic_vector	signed	signed(value)
unsigned/signed	std_logic_vector	std_logic_vector(value)
resize unsigned/signed	same numeric type	resize(value, new_width)

Arrays and ranges

signal data : std_logic_vector(7 downto 0);

data'length         -- 8
data'high           -- 7
data'low            -- 0
data'range          -- 7 downto 0
data'reverse_range  -- 0 to 7

FSM declarations

type state_t is (IDLE, RUN, DONE);
signal state_q : state_t := IDLE;
signal state_d : state_t;

Testbench clock and reset

constant CLOCK_PERIOD : time := 10 ns;
signal clk_s          : std_logic := '0';
signal reset_s        : std_logic := '1';

clk_s <= not clk_s after CLOCK_PERIOD / 2;

stimulus : process
begin
  wait until rising_edge(clk_s);
  wait until rising_edge(clk_s);
  reset_s <= '0';
  wait until rising_edge(clk_s);
  -- Tests
  finish;
end process;

Assertion

assert actual = expected
  report "Mismatch: expected=" & integer'image(expected) &
         " actual=" & integer'image(actual)
  severity failure;

Watchdog

watchdog : process
begin
  wait for 1 ms;
  assert false report "TIMEOUT" severity failure;
end process;

XSim command sequence

xvhdl.bat -2008 src\design.vhd
xvhdl.bat -2008 tb\tb_design.vhd
xelab.bat work.tb_design -s tb_design_sim
xsim.bat tb_design_sim -R

Basys 3 clock XDC

set_property PACKAGE_PIN W5 [get_ports clk_i]
set_property IOSTANDARD LVCMOS33 [get_ports clk_i]
create_clock -period 10.000 -name sys_clk [get_ports clk_i]

Essential Vivado reports

report_timing_summary
report_utilization
report_drc
report_clock_interaction
report_cdc

Before programming

• Regression passes.
• Correct top and part.
• Pins/I/O standards correct.
• Clock constrained.
• No unintended latches/multiple drivers.
• DRC passes.
• Setup and hold timing pass.
• CDC findings understood.