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Learning path

The path is organized around small deliverables. Do not wait until you know the entire language; each stage introduces only the syntax needed for the next circuit.

Stage 0 — Understand the target

Goal: distinguish software execution from hardware description.

Learn:

  • Concurrent assignments describe hardware operating in parallel.
  • A clocked process describes registers and the combinational logic feeding them.
  • Simulation time is not FPGA wall-clock time.
  • Synthesizable VHDL is a useful subset of the language.
  • The Basys 3 clock is 100 MHz, so one period is 10 ns.

Build: one switch directly drives one LED.

Verification: a two-line testbench changes the switch and asserts the LED.

Exit check:

  • I can explain what a signal driver is.
  • I know the difference between compile, elaborate, simulate, synthesize, implement, and program.

Stage 1 — Combinational logic

Goal: describe logic whose outputs depend only on current inputs.

Learn:

  • std_logic, std_logic_vector, unsigned, and signed.
  • Boolean operators and comparisons.
  • Selected and conditional assignments.
  • Complete combinational processes using process(all).
  • Default assignments and why missing branches infer latches.

Build:

  1. Basic gates.
  2. 2-to-1 and 4-to-1 multiplexers.
  3. A 4-bit adder with carry.
  4. A seven-segment hexadecimal decoder.

Verification:

  • Exhaust every input combination for small circuits.
  • Use a pure reference function for larger combinational circuits.

Stage 2 — Sequential logic

Goal: store state predictably.

Learn:

  • Rising-edge registers.
  • Synchronous reset and clock enable.
  • Counters, shift registers, edge detectors.
  • Signal assignment semantics: a signal updates after the process suspends.
  • Why you usually keep one real board clock and generate enables.

Build:

  1. An LED counter using a clock enable.
  2. A one-clock-cycle pulse on a button edge.
  3. A multiplexed four-digit display driver.

Verification:

  • Generate clock and reset centrally.
  • Check results relative to clock edges.
  • Add a timeout so a stuck test cannot run forever.

Stage 3 — Structure and reusable RTL

Goal: divide a design into understandable blocks.

Learn:

  • Direct entity instantiation.
  • Generics for widths and timing values.
  • Packages, subtypes, records, functions, and procedures.
  • Clear boundaries between control and datapath.
  • File organization and naming conventions.

Build: a parameterized timer with separate tick generator, counter, and display blocks.

Verification: reuse common clock/reset procedures and test multiple generic values.

Stage 4 — State machines and interfaces

Goal: design control logic deliberately.

Learn:

  • State diagrams and transition tables.
  • Moore versus Mealy outputs.
  • One-process and two-process FSM styles.
  • Safe default behavior and illegal-state recovery.
  • Handshakes: valid/ready and request/acknowledge.

Build: a traffic-light controller or a small UART transmitter.

Verification:

  • Assert legal transition sequences.
  • Exercise every state and transition.
  • Separate protocol driver, monitor, scoreboard, and DUT.

Stage 5 — Real FPGA engineering

Goal: make simulation results survive physical hardware.

Learn:

  • XDC pin properties and create_clock.
  • Setup/hold timing, clock uncertainty, WNS, and TNS.
  • Metastability, two-flop synchronizers, and clock-domain crossing.
  • Button debouncing.
  • Synthesis inference, resource sharing, DSP, block RAM, and fanout.
  • DRC, utilization, power, and timing reports.

Build: a robust user-interface design using buttons, switches, display, and UART.

Verification: include asynchronous stimulus and confirm the synchronization contract, without pretending RTL simulation can model metastability.

Stage 6 — Verification beyond hand-written cases

Goal: obtain repeatable evidence rather than attractive waveforms.

Learn:

  • Self-checking assertions and reference models.
  • File-driven vectors generated by Python or another model.
  • Constrained random stimulus and reproducible seeds.
  • Functional coverage and scoreboards.
  • Regression scripts and machine-readable results.
  • VUnit or OSVVM when a larger project justifies a framework.

Build: a regression suite that runs every test with one command and returns a failing exit status when any requirement is broken.

Suggested eight-week plan

Week Study Deliverable
1 Syntax and combinational logic Gates, mux, decoder
2 Numeric types and arithmetic Parameterized adder/ALU
3 Clocked logic Counter and clock-enable generator
4 Hierarchy and packages Four-digit display subsystem
5 FSMs Debounced controller
6 Testbench automation Self-checking regression
7 XDC and timing Clean implemented design
8 CDC and interfaces UART or multi-clock mini-project

How to study efficiently

For each circuit, keep four artifacts:

  1. Specification: interface, timing, reset behavior, corner cases.
  2. RTL: only the circuit that satisfies the specification.
  3. Testbench: an executable form of the expected behavior.
  4. Evidence: passing regression plus synthesis and timing reports.

If a design only works after observing a waveform and manually choosing convenient input times, the test is incomplete. Turn every discovered bug into an assertion or regression case.